The present invention relates to the field of semiconductor technology. Specifically, embodiments of the invention relate to FinFET (Fin Field Effect Transistor) devices, manufacturing methods, and related electronic devices.
With decreasing feature sizes of MOS devices, in its manufacturing process, effective control of the channel length of MOS devices become more challenging. Ultra-shallow junctions and abrupt junctions have improved the short channel effect in the core components. However, during the formation of ultra-shallow junctions and abrupt junctions, it is a challenging task to optimize a device structure to suppress the short channel effect and enhance the performance of MOS devices.
To overcome these problems, a variety of methods have been used to further improve the performance of MOS devices, such as pre-amorphous ion implantation (PAI) and stress technology. However, there are some shortcomings of these methods. For example, pre-amorphous ion implantation does not provide adequate control of the doping profiles of the source/drain regions of the MOS device, and stress techniques merely provide additional stress to the channel region of MOS devices to enhance their carrier mobility.